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Text File | 2009-09-09 | 19.5 KB | 761 lines

comment "Processor Type" config CPU_32 bool default y # Select CPU types depending on the architecture selected. This selects # which CPUs we support in the kernel image, and the compiler instruction # optimiser behaviour. # ARM610 config CPU_ARM610 bool "Support ARM610 processor" depends on ARCH_RPC select CPU_32v3 select CPU_CACHE_V3 select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V3 if MMU select CPU_TLB_V3 if MMU select CPU_PABRT_NOIFAR help The ARM610 is the successor to the ARM3 processor and was produced by VLSI Technology Inc. Say Y if you want support for the ARM610 processor. Otherwise, say N. # ARM7TDMI config CPU_ARM7TDMI bool "Support ARM7TDMI processor" depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4 help A 32-bit RISC microprocessor based on the ARM7 processor core which has no memory control unit and cache. Say Y if you want support for the ARM7TDMI processor. Otherwise, say N. # ARM710 config CPU_ARM710 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC default y if ARCH_CLPS7500 select CPU_32v3 select CPU_CACHE_V3 select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V3 if MMU select CPU_TLB_V3 if MMU select CPU_PABRT_NOIFAR help A 32-bit RISC microprocessor based on the ARM7 processor core designed by Advanced RISC Machines Ltd. The ARM710 is the successor to the ARM610 processor. It was released in July 1994 by VLSI Technology Inc. Say Y if you want support for the ARM710 processor. Otherwise, say N. # ARM720T config CPU_ARM720T bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X select CPU_32v4T select CPU_ABRT_LV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4 select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WT if MMU select CPU_TLB_V4WT if MMU help A 32-bit RISC processor with 8kByte Cache, Write Buffer and MMU built around an ARM7TDMI core. Say Y if you want support for the ARM720T processor. Otherwise, say N. # ARM740T config CPU_ARM740T bool "Support ARM740T processor" if ARCH_INTEGRATOR depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V3 # although the core is v4t select CPU_CP15_MPU help A 32-bit RISC processor with 8KB cache or 4KB variants, write buffer and MPU(Protection Unit) built around an ARM7TDMI core. Say Y if you want support for the ARM740T processor. Otherwise, say N. # ARM9TDMI config CPU_ARM9TDMI bool "Support ARM9TDMI processor" depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU select CPU_PABRT_NOIFAR select CPU_CACHE_V4 help A 32-bit RISC microprocessor based on the ARM9 processor core which has no memory control unit and cache. Say Y if you want support for the ARM9TDMI processor. Otherwise, say N. # ARM920T config CPU_ARM920T bool "Support ARM920T processor" depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 select CPU_32v4T select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WBI if MMU help The ARM920T is licensed to be produced by numerous vendors, and is used in the Maverick EP9312 and the Samsung S3C2410. More information on the Maverick EP9312 at <http://linuxdevices.com/products/PD2382866068.html>. Say Y if you want support for the ARM920T processor. Otherwise, say N. # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695 default y if ARCH_LH7A40X || ARCH_KS8695 select CPU_32v4T select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WBI if MMU help The ARM922T is a version of the ARM920T, but with smaller instruction and data caches. It is used in Altera's Excalibur XA device family and Micrel's KS8695 Centaur. Say Y if you want support for the ARM922T processor. Otherwise, say N. # ARM925T config CPU_ARM925T bool "Support ARM925T processor" if ARCH_OMAP1 depends on ARCH_OMAP15XX default y if ARCH_OMAP15XX select CPU_32v4T select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WBI if MMU help The ARM925T is a mix between the ARM920T and ARM926T, but with different instruction and data caches. It is used in TI's OMAP device family. Say Y if you want support for the ARM925T processor. Otherwise, say N. # ARM926T config CPU_ARM926T bool "Support ARM926T processor" depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \ MACH_VERSATILE_AB || ARCH_OMAP730 || \ ARCH_OMAP16XX || MACH_REALVIEW_EB || \ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 || ARCH_MXC default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \ ARCH_OMAP730 || ARCH_OMAP16XX || \ ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \ ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \ ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \ ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \ ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2 select CPU_32v5 select CPU_ABRT_EV5TJ select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WBI if MMU help This is a variant of the ARM920. It has slightly different instruction sequences for cache and TLB operations. Curiously, there is no documentation on it at the ARM corporate website. Say Y if you want support for the ARM926T processor. Otherwise, say N. # ARM940T config CPU_ARM940T bool "Support ARM940T processor" if ARCH_INTEGRATOR depends on !MMU select CPU_32v4T select CPU_ABRT_NOMMU select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MPU help ARM940T is a member of the ARM9TDMI family of general- purpose microprocessors with MPU and separate 4KB instruction and 4KB data cases, each with a 4-word line length. Say Y if you want support for the ARM940T processor. Otherwise, say N. # ARM946E-S config CPU_ARM946E bool "Support ARM946E-S processor" if ARCH_INTEGRATOR depends on !MMU select CPU_32v5 select CPU_ABRT_NOMMU select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MPU help ARM946E-S is a member of the ARM9E-S family of high- performance, 32-bit system-on-chip processor solutions. The TCM and ARMv5TE 32-bit instruction set is supported. Say Y if you want support for the ARM946E-S processor. Otherwise, say N. # ARM1020 - needs validating config CPU_ARM1020 bool "Support ARM1020T (rev 0) processor" depends on ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WBI if MMU help The ARM1020 is the 32K cached version of the ARM10 processor, with an addition of a floating-point unit. Say Y if you want support for the ARM1020 processor. Otherwise, say N. # ARM1020E - needs validating config CPU_ARM1020E bool "Support ARM1020E processor" depends on ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR select CPU_CACHE_V4WT select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WBI if MMU depends on n # ARM1022E config CPU_ARM1022 bool "Support ARM1022E processor" depends on ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV4T select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU # can probably do better select CPU_TLB_V4WBI if MMU help The ARM1022E is an implementation of the ARMv5TE architecture based upon the ARM10 integer core with a 16KiB L1 Harvard cache, embedded trace macrocell, and a floating-point unit. Say Y if you want support for the ARM1022E processor. Otherwise, say N. # ARM1026EJ-S config CPU_ARM1026 bool "Support ARM1026EJ-S processor" depends on ARCH_INTEGRATOR select CPU_32v5 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU # can probably do better select CPU_TLB_V4WBI if MMU help The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture based upon the ARM10 integer core. Say Y if you want support for the ARM1026EJ-S processor. Otherwise, say N. # SA110 config CPU_SA110 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI select CPU_32v3 if ARCH_RPC select CPU_32v4 if !ARCH_RPC select CPU_ABRT_EV4 select CPU_PABRT_NOIFAR select CPU_CACHE_V4WB select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_V4WB if MMU select CPU_TLB_V4WB if MMU help The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and is available at five speeds ranging from 100 MHz to 233 MHz. More information is available at <http://developer.intel.com/design/strong/sa110.htm>. Say Y if you want support for the SA-110 processor. Otherwise, say N. # SA1100 config CPU_SA1100 bool depends on ARCH_SA1100 default y select CPU_32v4 select CPU_ABRT_EV4 select CPU_PABRT_NOIFAR select CPU_CACHE_V4WB select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_TLB_V4WB if MMU # XScale config CPU_XSCALE bool depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000 default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_TLB_V4WBI if MMU # XScale Core Version 3 config CPU_XSC3 bool depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_TLB_V4WBI if MMU select IO_36 # Feroceon config CPU_FEROCEON bool depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0 default y select CPU_32v5 select CPU_ABRT_EV5T select CPU_PABRT_NOIFAR select CPU_CACHE_VIVT select CPU_CP15_MMU select CPU_COPY_FEROCEON if MMU select CPU_TLB_FEROCEON if MMU config CPU_FEROCEON_OLD_ID bool "Accept early Feroceon cores with an ARM926 ID" depends on CPU_FEROCEON && !CPU_ARM926T default y help This enables the usage of some old Feroceon cores for which the CPU ID is equal to the ARM926 ID. Relevant for Feroceon-1850 and early Feroceon-2850. # ARMv6 config CPU_V6 bool "Support ARM V6 processor" depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MXC || ARCH_MSM || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 default y if ARCH_MX3 default y if ARCH_MSM select CPU_32v6 select CPU_ABRT_EV6 select CPU_PABRT_NOIFAR select CPU_CACHE_V6 select CPU_CACHE_VIPT select CPU_CP15_MMU select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V6 if MMU # ARMv6k config CPU_32v6K bool "Support ARM V6K processor extensions" if !SMP depends on CPU_V6 default y if SMP && !ARCH_MX3 help Say Y here if your ARMv6 processor supports the 'K' extension. This enables the kernel to use some instructions not present on previous processors, and as such a kernel build with this enabled will not boot on processors with do not support these instructions. # ARMv7 config CPU_V7 bool "Support ARM V7 processor" depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP3 || ARCH_MXC select CPU_32v6K select CPU_32v7 select CPU_ABRT_EV7 select CPU_PABRT_IFAR select CPU_CACHE_V7 select CPU_CACHE_VIPT select CPU_CP15_MMU select CPU_HAS_ASID if MMU select CPU_COPY_V6 if MMU select CPU_TLB_V7 if MMU # Figure out what processor architecture version we should be using. # This defines the compiler instruction set which depends on the machine type. config CPU_32v3 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v4 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v4T bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v5 bool select TLS_REG_EMUL if SMP || !MMU select NEEDS_SYSCALL_FOR_CMPXCHG if SMP config CPU_32v6 bool select TLS_REG_EMUL if !CPU_32v6K && !MMU config CPU_32v7 bool # The abort model config CPU_ABRT_NOMMU bool config CPU_ABRT_EV4 bool config CPU_ABRT_EV4T bool config CPU_ABRT_LV4T bool config CPU_ABRT_EV5T bool config CPU_ABRT_EV5TJ bool config CPU_ABRT_EV6 bool config CPU_ABRT_EV7 bool config CPU_PABRT_IFAR bool config CPU_PABRT_NOIFAR bool # The cache model config CPU_CACHE_V3 bool config CPU_CACHE_V4 bool config CPU_CACHE_V4WT bool config CPU_CACHE_V4WB bool config CPU_CACHE_V6 bool config CPU_CACHE_V7 bool config CPU_CACHE_VIVT bool config CPU_CACHE_VIPT bool if MMU # The copy-page model config CPU_COPY_V3 bool config CPU_COPY_V4WT bool config CPU_COPY_V4WB bool config CPU_COPY_FEROCEON bool config CPU_COPY_V6 bool # This selects the TLB model config CPU_TLB_V3 bool help ARM Architecture Version 3 TLB. config CPU_TLB_V4WT bool help ARM Architecture Version 4 TLB with writethrough cache. config CPU_TLB_V4WB bool help ARM Architecture Version 4 TLB with writeback cache. config CPU_TLB_V4WBI bool help ARM Architecture Version 4 TLB with writeback cache and invalidate instruction cache entry. config CPU_TLB_FEROCEON bool help Feroceon TLB (v4wbi with non-outer-cachable page table walks). config CPU_TLB_V6 bool config CPU_TLB_V7 bool endif config CPU_HAS_ASID bool help This indicates whether the CPU has the ASID register; used to tag TLB and possibly cache entries. config CPU_CP15 bool help Processor has the CP15 register. config CPU_CP15_MMU bool select CPU_CP15 help Processor has the CP15 register, which has MMU related registers. config CPU_CP15_MPU bool select CPU_CP15 help Processor has the CP15 register, which has MPU related registers. # # CPU supports 36-bit I/O # config IO_36 bool comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON default y help Say Y if you want to include kernel support for running user space Thumb binaries. The Thumb instruction set is a compressed form of the standard ARM instruction set resulting in smaller binaries at the expense of slightly less efficient code. If you don't know what this all is, saying Y is a safe choice. config ARM_THUMBEE bool "Enable ThumbEE CPU extension" depends on CPU_V7 help Say Y here if you have a CPU with the ThumbEE extension and code to make use of it. Say N for code that can run on CPUs without ThumbEE. config CPU_BIG_ENDIAN bool "Build big-endian kernel" depends on ARCH_SUPPORTS_BIG_ENDIAN help Say Y if you plan on running a kernel in big-endian mode. Note that your board must be properly built and your board port must properly enable any big-endian related features of your chipset/board/processor. config CPU_HIGH_VECTOR depends on !MMU && CPU_CP15 && !CPU_ARM740T bool "Select the High exception vector" default n help Say Y here to select high exception vector(0xFFFF0000~). The exception vector can be vary depending on the platform design in nommu mode. If your platform needs to select high exception vector, say Y. Otherwise or if you are unsure, say N, and the low exception vector (0x00000000~) will be used. config CPU_ICACHE_DISABLE bool "Disable I-Cache (I-bit)" depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) help Say Y here to disable the processor instruction cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_DISABLE bool "Disable D-Cache (C-bit)" depends on CPU_CP15 help Say Y here to disable the processor data cache. Unless you have a reason not to or are unsure, say N. config CPU_DCACHE_SIZE hex depends on CPU_ARM740T || CPU_ARM946E default 0x00001000 if CPU_ARM740T default 0x00002000 # default size for ARM946E-S help Some cores are synthesizable to have various sized cache. For ARM946E-S case, it can vary from 0KB to 1MB. To support such cache operations, it is efficient to know the size before compile time. If your SoC is configured to have a different size, define the value here with proper conditions. config CPU_DCACHE_WRITETHROUGH bool "Force write through D-cache" depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE default y if CPU_ARM925T help Say Y here to use the data cache in writethrough mode. Unless you specifically require this or are unsure, say N. config CPU_CACHE_ROUND_ROBIN bool "Round robin I and D cache replacement algorithm" depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) help Say Y here to use the predictable round-robin cache replacement policy. Unless you specifically require this or are unsure, say N. config CPU_BPREDICT_DISABLE bool "Disable branch prediction" depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 help Say Y here to disable branch prediction. If unsure, say N. config TLS_REG_EMUL bool help An SMP system using a pre-ARMv6 processor (there are apparently a few prototypes like that in existence) and therefore access to that required register must be emulated. config HAS_TLS_REG bool depends on !TLS_REG_EMUL default y if SMP || CPU_32v7 help This selects support for the CP15 thread register. It is defined to be available on some ARMv6 processors (including all SMP capable ARMv6's) or later processors. User space may assume directly accessing that register and always obtain the expected value only on ARMv7 and above. config NEEDS_SYSCALL_FOR_CMPXCHG bool help SMP on a pre-ARMv6 processor? Well OK then. Forget about fast user space cmpxchg support. It is just not possible. config OUTER_CACHE bool default n config CACHE_FEROCEON_L2 bool "Enable the Feroceon L2 cache controller" depends on ARCH_KIRKWOOD || ARCH_MV78XX0 default y select OUTER_CACHE help This option enables the Feroceon L2 cache controller. config CACHE_FEROCEON_L2_WRITETHROUGH bool "Force Feroceon L2 cache write through" depends on CACHE_FEROCEON_L2 default n help Say Y here to use the Feroceon L2 cache in writethrough mode. Unless you specifically require this, say N for writeback mode. config CACHE_L2X0 bool "Enable the L2x0 outer cache controller" depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 default y select OUTER_CACHE help This option enables the L2x0 PrimeCell. config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 default y select OUTER_CACHE help This option enables the L2 cache on XScale3.